Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Proceedings of the 44th annual Design Automation Conference
Measuring deep metastability and its effect on synchronizer performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchronizer Behavior and Analysis
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Synchronization and Arbitration in Digital Systems
Synchronization and Arbitration in Digital Systems
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Chip designs have an increasing number of independent clock domains. Synchronizer circuits are used to facilitate reliable data transfers between these clock domains. The task of these synchronizers is inherently prone to the occasional, statistically random, failure. These failures are frequently quantified by the synchronizers' mean time between failures, MTBF. The MTBF becomes worse at an exponential rate with increasing frequency. In contrast, the MTBF improves exponentially as more latches are cascaded to form the synchronizer, but at the cost of increasing the data transfer latency. Thus, selecting the number of latch stages to employ in the synchronizer is a trade-off between reliability and latency. We present equations for accurate estimation of the MTBF of multi-latch synchronizers, combined with an error analysis of these equations. We compare MTBF estimates obtained by using these equations to estimates gathered from comprehensive simulation analysis, and show that error terms are not insignificant. We provide a detailed description of all the assumptions that we have made in both the formulation of the MTBF equations and the circuit simulation environment.