Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital systems engineering
Test and Reliability: Partners in IC Manufacturing, Part 1
IEEE Design & Test
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
On the Detectability of Scan Chain Internal Faults An Industrial Case Study
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Analysis of Resistive Open Defects in a Synchronizer
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Testing of Synchronizers in Asynchronous FIFO
Journal of Electronic Testing: Theory and Applications
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This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer. Simulation results demonstrate that bridging fault effects of the synchronizer depend on fault location, bridging resistance value, the input signal (rising and falling), and the time of input signal application. The issues of bridging fault behavior under the consideration of process variation, and the relationship between bridging faults and the synchronizer failure mechanisms are also discussed.