Reliable High-Speed Arbitration and Synchronization
IEEE Transactions on Computers
Proceedings of the eighth annual ACM Symposium on Principles of distributed computing
Buffer-optimal constructions of 1-writer multireader multivalued atomic shared variables
Journal of Parallel and Distributed Computing
Concurrent Reading While Writing
ACM Transactions on Programming Languages and Systems (TOPLAS)
Monitors: an operating system structuring concept
Communications of the ACM
The Theory and Practice of Concurrency
The Theory and Practice of Concurrency
Hardware Design and Petri Nets
Hardware Design and Petri Nets
Proceedings of the 2nd International Workshop on Distributed Algorithms
How to Construct an Atomic Variable (Extended Abstract)
Proceedings of the 3rd International Workshop on Distributed Algorithms
The Formal Classification and Verification of Simpson's 4-Slot Asynchronous Communication Mechanism
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
Space-optimum Conflict-free Construction of 1-Writer 1-Reader Multivalued Atomic Variable
WDAG '94 Proceedings of the 8th International Workshop on Distributed Algorithms
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Ramifications of metastability in bit variables explored via Simpson’s 4-slot mechanism
Formal Aspects of Computing
Register Communication between Mutually Asynchronous Domains
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
Analysis of the four-slot mechanism
1FACS'96 Proceedings of the 1st BCS-FACS conference on Northern Formal Methods
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We demonstrate that the safe register abstraction is an inappropriate model of a shared bit variable in an ACM. This is due to the phenomenon of metastability and the way that circuits are engineered to reduce the probability of it propagating. We give a bit model that takes the engineered restrictions into account and which is therefore stronger than the safe bit model. With our bit model we show that some impossibility results concerning ACMs which are based on safe bit models are pessimistic. We establish this using the CSP process algebra and the FDR2 model-checker, by investigating the impact of various models of shared bits on different wait-free protocols, including Lamport's regular register, Simpson's 4-slot ACM, Kirousis et al.'s ACM, Tromp's Atomic Bit and 4-Track ACMs, and Haldar and Subramanian's ACM. We show how these protocols can fail in the presence of rereadable metastability.