When reconfigurable architecture meets network-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Advances in c-based parallel design of MP-SOCs
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Power aware reconfigurable multiprocessor for elliptic curve cryptography
Proceedings of the conference on Design, automation and test in Europe
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Run-time reconfigurability in embedded multiprocessors
ACM SIGARCH Computer Architecture News
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
Redsharc: a programming model and on-chip network for multi-core systems on a programmable chip
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Dual partitioning multicasting for high-performance on-chip networks
Journal of Parallel and Distributed Computing
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The TRIPS architecture seeks to deliver system-level configurability to applications and runtime systems. It does so by employing the concept of polymorphism, which permits the runtime system to configure the hardware execution resources to match the mode of execution and demands of the compiler and application.