Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors

  • Authors:

  • Srinivasan Murali;David Atienza;Paolo Meloni;Salvatore Carta;Luca Benini;Giovanni De Micheli;Luigi Raffo

  • Affiliations:

  • Computer Science Laboratory, Stanford University, Stanford, CA;Integrated Systems Laboratory, EPFL, Lausanne, Switzerland and Computer Architecture and Automation Department, Complutense University of Madrid, Madrid, Spain;Dipartimento di Ingegneria Elettrica ed Elettronica, University of Cagliari, Cagliari, Italy;Computer Science Department, University of Cagliari, Cagliari, Italy;Dipartimento Elettronica Informatica E Sistemisfica, University of Bologna, Bologna, Italy;Integrated Systems Centre, EPFL, Lausanne, Switzerland;Dipartimento di Ingegneria Elettrica ed Elettronica, University of Cagliari, Cagliari, Italy

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable behavior is essential for proper system operation. In CMPs, general-purpose processor cores are used to run software tasks of different applications and the communication between the cores cannot be precharacterized. Designing an efficient network-on-chip (NoC)-based interconnect with predictable performance is thus a challenging task. In this paper, we address the important design issue of synthesizing the most power efficient NoC interconnect for CMPs, providing guaranteed optimum throughput and predictable performance for any application to be executed on the CMP. In our synthesis approach, we use accurate delay and power models for the network components (switches and links) that are obtained from layouts of the components using industry standard tools. The synthesis approach utilizes the floorplan knowledge of the NoC to detect timing violations on the NoC links early in the design cycle. This leads to a faster design cycle and quicker design convergence across the high-level synthesis approach and the physical implementation of the design. We validate the design flow predictability of our proposed approach by performing a layout of the NoC synthesized for a 25-core CMP. Our approach maintains the regular and predictable structure of the NoC and is applicable in practice to existing NoC architectures.