Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Design for manufacturability in submicron domain
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
How VSIA Answers the SOC Dilemma
Computer
Core Design and System-on-a-Chip Integration
IEEE Design & Test
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
An IP-based on-chip packet-switched network
Networks on chip
Topology optimization for application-specific networks-on-chip
Proceedings of the 2004 international workshop on System level interconnect prediction
VHDL-based simulation environment for Proteo NoC
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Applying CDMA technique to network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
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Network-on-Chip will be one of the cornerstones of future electronics. At Tampere University of Technology we have been working on the development of our own proposal for a flexible on-chip communication network, called Proteo. Proteo introduces the concept of an open library of communication components that can be selected and configured to build highly-customized networks-on-chip. The designer of a new System-on-Chip platform starts with a description of the hardware components of the system and an abstract model of the problem application, and with the help of the Proteo software tools, obtains a synthesizable instance of a packet-switching network that, ideally, meets his requirements. The constraints placed on the type of designs that may use Proteo are minimal and an important part of the process should be automated. In this article we introduce the philosophy behind the project in relation to fundamental deep submicron technology problems, and some of our initial results.