System-on-Chip Testability Using LSSD Scan Structures
IEEE Design & Test
Dynamically Reconfigurable Cores
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Issues in the development of a practical NoC: the Proteo concept
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
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ICOSSE'06 Proceedings of the 5th WSEAS international conference on System science and simulation in engineering
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IBM's experience with core based designs and the methodology support required for system on a chip (SOC) designs is discussed. An overview of the different styles of SOC designs used in the industry today, the tradeoffs made when cores were designed, the ASIC design process used, and a prototype hardware software cosimulation system developed for the IBM PowerPC (tm) core are also described. Actual SOC designs created using these methods and implemented in a 0.36 micron technology will be referenced to illustrate specific points. The designs include two ASICs with embedded peripheral component interface (PCI) cores, an ASIC containing both an embedded PowerPC microprocessor and a mixed signal memory controller core, and an ASIC containing a RAMDAC core.