High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Hardware/software synthesis of formal specifications in codesign of embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
The Codesign of Embedded Systems: A Unified Hardware/Software Representation
The Codesign of Embedded Systems: A Unified Hardware/Software Representation
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
Introducing Core-Based System Design
IEEE Design & Test
Core Design and System-on-a-Chip Integration
IEEE Design & Test
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
The IEC/IEEE Train Communication Network
IEEE Micro
An industrial view of electronic design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The specifications analysis for an MVB (Multifunction Vehicle Bus) bus administrator showed that system-on-a-chip strategies should be adopted to cope with its great complexity. Particularly, a new hardware/software codesign methodology has been followed. Its main concept is that the MVB devices (the bus administrator itself and the less complex devices) constitute a "progressive family". This notion establishes a functional partition that helps to generate the behavioral design: 14 operational blocks and a special memory for the communication data. The whole architecture has been coded in SystemC, not only for verification purposes, but also to set the start point in hardware/software partitioning. After validating this executable description by simulation, estimations about cost and performance in both, hardware and software, have been made. From these, an optimum hardware-software architecture has been obtained. As a result, the electronic platform for the Master device has been generated on an FPGA.