Core Design and System-on-a-Chip Integration
IEEE Design & Test
Pipeline morphing and virtual pipelines
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Self Controlling Dynamic Reconfiguration: A Case Study
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Artificial Neural Network Implementation on a Fine-Grained FPGA
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Fast Reconfigurable Crossbar Switching in FPGAs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Use of Reconfigurability in Variable-Length Code Detection at Video Rates
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Dynamic reconfiguration in JPEG2000 hardware architecture
KES'11 Proceedings of the 15th international conference on Knowledge-based and intelligent information and engineering systems - Volume Part III
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Dynamic reconfiguration of digital circuits on FPGAs has been an area of active research for the past decade. The identification of generic classes of circuits that would benefit from being dynamically reconfigured remains a key, open problem. We report on an investigation of the application of dynamic reconfiguration to programmable, multi-function cores (PMCs). An abstract analysis of the technique is included to emphasise the generality of the methodology. Empirical results for a case study involving a universal asynchronous receiver and transmitter (UART) are presented. We show that significant improvements in area efficiency and the operating speeds of the circuits are achieved. Furthermore, the results indicate the potential for reducing the power consumption of the circuits.