A dynamically reconfigurable adaptive viterbi decoder
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Dynamically Reconfigurable Cores
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A Run-Time Reconfigurable Plug-In for the Winamp MP3 Player
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
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Reconfigurable hardware components such as Field Programmable Gate Arrays (FPGAs) are used more and more in embedded systems, since such components offer a sufficient capacity for a complete System on a Chip (SoC) with a high degree of flexibility. In order to use efficiently the dynamic reconfiguration possibility on such components, there is a need to exploit this feature on complex real-world applications. This paper proposes a dynamically reconfigurable architecture for JPEG2000 application. The dynamic reconfiguration of JPEG2000 enables us to use hardware resources more efficiently which reduces power consumption and increases the frame rate of image compression.