SPLASH: Stanford parallel applications for shared-memory
ACM SIGARCH Computer Architecture News
Automatic characterization and modeling of power consumption in static RAMs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
Classifying Software-Based Cache Coherence Solutions
IEEE Software
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Impulse: Building a Smarter Memory Controller
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Software for multiprocessor networks on chip
Networks on chip
High Performance Memory Systems
High Performance Memory Systems
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Sun's big splash [Niagara microprocessor chip]
IEEE Spectrum
Energy efficient synchronization techniques for embedded architectures
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Comparison of memory write policies for NoC based multicore cache coherent systems
Proceedings of the conference on Design, automation and test in Europe
Extending open core protocol to support system-level cache coherence
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Low-power inter-core communication through cache partitioning in embedded multiprocessors
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
On the energy-efficiency of software transactional memory
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Microprocessors & Microsystems
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
STM versus lock-based systems: an energy consumption perspective
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Journal of Parallel and Distributed Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A minimalist cache coherent MPSoC designed for FPGAs
International Journal of High Performance Systems Architecture
On chip cache quantitative optimization approach: study in chip multi-processor design
HPCA'09 Proceedings of the Second international conference on High Performance Computing and Applications
Energy and throughput efficient transactional memory for embedded multicore systems
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis
International Journal of Embedded and Real-Time Communication Systems
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Shared memory is a common interprocessor communication paradigm for single-chip multiprocessor platforms. Snoop-based cache coherence is a very successful technique that provides a clean shared-memory programming abstraction in general-purpose chip multiprocessors, but there is no consensus on its usage in resource-constrained multiprocessor systems on chips (MPSoCs) for embedded applications. This work aims at providing a comparative energy and performance analysis of cache-coherence support schemes in MPSoCs. Thanks to the use of a complete multiprocessor simulation platform, which relies on accurate technology-homogeneous power models, we were able to explore different cache-coherent shared-memory communication schemes for a number of cache configurations and workloads.