On chip cache quantitative optimization approach: study in chip multi-processor design

Authors:
Chi Zhang;Xiang Wang
Affiliations:
School of Electronic and Information Engineering, Beihang University, Beijing, China;School of Electronic and Information Engineering, Beihang University, Beijing, China
Venue:
HPCA'09 Proceedings of the Second international conference on High Performance Computing and Applications
Year:
2009

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Abstract

The nanoelectroincs era promotes multi-core processor (or chip multiprocessor, CMP) improvements with a good deal of both opportunities and challenges. In CMP systems based on SMP organization, cache is much more important than before because performance promoted by multiprocessor is easily degraded by memory latency in shared symmetric multiprocessors. A quantitative optimization cache design is presented in SMP based CMP systems. Cache design strategies in uniprocessor systems are implemented in multiprocessor simulator by executing parallel programs for different number of processors. Evaluation result shows that designing principles in uniprocessor are partly applicable to multiprocessor systems while some traditional designs deteriorate system performance. Increasing cache sizes results in hit rates augment from 15.01% to 43.83% in various simulation conditions, while hit rates is an extremal function for block size. For large caches (128KB), Random algorithm overrides LRU for 6.041% hit rate at most.