Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Cycle-accurate power analysis for multiprocessor systems-on-a-chip
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Energy reduction in multiprocessor systems using transactional memory
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Software and the Concurrency Revolution
Queue - Multiprocessors
Cache coherence tradeoffs in shared-memory MPSoCs
ACM Transactions on Embedded Computing Systems (TECS)
Energy efficient synchronization techniques for embedded architectures
Proceedings of the 18th ACM Great Lakes symposium on VLSI
DISC'06 Proceedings of the 20th international conference on Distributed Computing
The implications of shared data synchronization techniques on multi-core energy efficiency
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
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The shift towards multicore processors and the well-known drawbacks imposed by lock-based synchronization have forced researchers to devise new alternatives for building concurrent software, of which transactional memory is a promising one. This work presents a comprehensive study on the energy consumption of a state-of-the-art STM (Software Transactional Memory) implementation using STAMP, a representative set of transactional workloads, comparing it to its lock-based counterpart. Our results show that STM can be up to 22x (~3x on average) more energy-inefficient when compared to locks. This work is a novel step towards a better understanding of the energy behavior of STM systems.