Energy efficient synchronization techniques for embedded architectures

  • Authors:
  • Cesare Ferri;Amber Viescas;Tali Moreshet;R. Iris Bahar;Maurice Herlihy

  • Affiliations:
  • Brown University, Providence, RI, USA;Swarthmore College, Swarthmore, PA, USA;Swarthmore College, Swarthmore, PA, USA;Brown University, Providence, RI, USA;Brown University, Providence, RI, USA

  • Venue:
  • Proceedings of the 18th ACM Great Lakes symposium on VLSI
  • Year:
  • 2008

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Abstract

We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. We focus on simple hardware accelerators for common software synchronization patterns. We compare the energy efficiency of a range of shared memory benchmarks using both spin-locks and a simple hardware transactional memory. In most cases, transactional memory provides both significantly reduced energy consumption and increased throughput. We also consider applications that employ concurrency patterns based on semaphores, such as pipelines and barriers. We propose and evaluate a novel energy-efficient hardware semaphore construction in which cores spin on local scratchpad memory, reducing the load on the shared bus.