Cache coherence tradeoffs in shared-memory MPSoCs
ACM Transactions on Embedded Computing Systems (TECS)
Fpga-based prototype of a pram-on-chip processor
Proceedings of the 5th conference on Computing frontiers
Web search using mobile cores: quantifying and mitigating the price of efficiency
Proceedings of the 37th annual international symposium on Computer architecture
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A new microprocessor chip was developed by Sun Microsystems Inc. that is intended for volume servers that are at the heart of data centers running the information and Web processing for businesses, universities, hospitals, factories, and the like. The new chip, called Niagara for the torrent of data and instructions that flow between the chip and its memory, was designed from the ground up to do away with the impact of latency - the idle time a microprocessor spends for data or instructions to arrive from memory. The goal of the design is to build a microprocessor that works 10 times as efficiently as existing devices for processing applications at half the power consumption of comparable devices. This paper discusses the development of the Niagara chip and its advantages from other microprocessors.