EazyHTM: eager-lazy hardware transactional memory

  • Authors:

  • Saša Tomić;Cristian Perfumo;Chinmay Kulkarni;Adrià Armejach;Adrián Cristal;Osman Unsal;Tim Harris;Mateo Valero

  • Affiliations:

  • BSC-Microsoft Research Centre and Universitat Politècnica de Catalunya;BSC-Microsoft Research Centre and Universitat Politècnica de Catalunya;BSC-Microsoft Research Centre, BITS Pilani;BSC-Microsoft Research Centre and Universitat Politècnica de Catalunya;BSC-Microsoft Research Centre;BSC-Microsoft Research Centre;Microsoft Research Cambridge;BSC-Microsoft Research Centre

  • Venue:
  • Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2009

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Abstract

Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overheads than implementations in software, and refinements in conflict management strategies for HTM allow for even larger improvements. In particular, lazy conflict management has been shown to deliver better performance, but it has hitherto required complex protocols and implementations. In this paper we show a new scalable HTM architecture that performs comparably to the state-of-the-art and can be implemented by minor modifications to the MESI protocol rather than re-engineering it from the ground up. Our approach detects conflicts eagerly while a transaction is running, but defers the resolution lazily until commit time. We evaluate this EAger-laZY system, EazyHTM, by comparing it with the Scalable-TCC-like approach and a system employing ideal lazy conflict management with a zero-cycle transaction validation and fully-parallel commits. We show that EazyHTM performs on average 7% faster than Scalable-TCC. In addition, EazyHTM has fast commits and aborts, can commit in parallel even if there is only one directory present, and does not suffer from cascading waits.