Enforcing isolation and ordering in STM

  • Authors:

  • Tatiana Shpeisman;Vijay Menon;Ali-Reza Adl-Tabatabai;Steven Balensiefer;Dan Grossman;Richard L. Hudson;Katherine F. Moore;Bratin Saha

  • Affiliations:

  • Intel Corporation, Santa Clara, CA;Intel Corporation, Santa Clara, CA;Intel Corporation, Santa Clara, CA;University of Washington, Seattle, WA;University of Washington, Seattle, WA;Intel Corporation, Santa Clara, CA;University of Washington, Seattle, WA;Intel Corporation, Santa Clara, CA

  • Venue:
  • Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
  • Year:
  • 2007

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Abstract

Transactional memory provides a new concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. High-performance software transactional memory (STM) implementations thus far provide weak atomicity: Accessing shared data both inside and outside a transaction can result in unexpected, implementation-dependent behavior. To guarantee isolation and consistent ordering in such a system, programmers are expected to enclose all shared-memory accesses inside transactions. A system that provides strong atomicity guarantees isolation even in the presence of threads that access shared data outside transactions. A strongly-atomic system also orders transactions with conflicting non-transactional memory operations in a consistent manner. In this paper, we discuss some surprising pitfalls of weak atomicity, and we present an STM system that avoids these problems via strong atomicity. We demonstrate how to implement non-transactional data accesses via efficient read and write barriers, and we present compiler optimizations that further reduce the overheads of these barriers. We introduce a dynamic escape analysis that differentiates private and public data at runtime to make barriers cheaper and a static not-accessed-in-transaction analysis that removes many barriers completely. Our results on a set of Java programs show that strong atomicity can be implemented efficiently in a high-performance STM system.