Transactional memory: architectural support for lock-free data structures
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Coherent network interfaces for fine-grain communication
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
Language support for lightweight transactions
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Transactional Memory Coherence and Consistency
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McRT-STM: a high performance software transactional memory system for a multi-core runtime
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Compiler and runtime support for efficient software transactional memory
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Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Architectural Support for Software Transactional Memory
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Making the fast case common and the uncommon case simple in unbounded transactional memory
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An effective hybrid transactional memory system with strong isolation guarantees
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MetaTM/TxLinux: transactional memory for an operating system
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An integrated hardware-software approach to flexible transactional memory
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PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
The OpenTM Transactional Application Programming Interface
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
A Scalable, Non-blocking Approach to Transactional Memory
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
RingSTM: scalable transactions with a single atomic instruction
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Flexible Decoupled Transactional Memory Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Software Transactional Memory: Why Is It Only a Research Toy?
Queue - The Concurrency Problem
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Notary: Hardware techniques to enhance signatures
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FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
PACT '09 Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
NOrec: streamlining STM by abolishing ownership records
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FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Eigenbench: A simple exploration tool for orthogonal TM characteristics
IISWC '10 Proceedings of the IEEE International Symposium on Workload Characterization (IISWC'10)
DISC'06 Proceedings of the 20th international conference on Distributed Computing
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DISC'05 Proceedings of the 19th international conference on Distributed Computing
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ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
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Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware. We propose that hardware to accelerate software transactional memory (STM) can reside outside an unmodified commodity processor core, thereby substantially reducing implementation costs. This paper introduces Transactional Memory Acceleration using Commodity Cores (TMACC), a hardware-accelerated TM system that does not modify the processor, caches, or coherence protocol. We present a complete hardware implementation of TMACC using a rapid prototyping platform. Using this hardware, we implement two unique conflict detection schemes which are accelerated using Bloom filters on an FPGA. These schemes employ novel techniques for tolerating the latency of fine-grained asynchronous communication with an out-of-core accelerator. We then conduct experiments to explore the feasibility of accelerating TM without modifying existing system hardware. We show that, for all but short transactions, it is not necessary to modify the processor to obtain substantial improvement in TM performance. In these cases, TMACC outperforms an STM by an average of 69% in applications using moderate-length transactions, showing maximum speedup within 8% of an upper bound on TM acceleration. Overall, we demonstrate that hardware can substantially accelerate the performance of an STM on unmodified commodity processors.