Algorithms for scalable synchronization on shared-memory multiprocessors
ACM Transactions on Computer Systems (TOCS)
Speculative lock elision: enabling highly concurrent multithreaded execution
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
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Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
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Proceedings of the twenty-sixth annual ACM symposium on Principles of distributed computing
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ICPP '08 Proceedings of the 2008 37th International Conference on Parallel Processing
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Proceedings of the 4th ACM European conference on Computer systems
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Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
The Art of Multiprocessor Programming
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Proceedings of the 29th ACM SIGACT-SIGOPS symposium on Principles of distributed computing
Transactional Memory, 2nd Edition
Transactional Memory, 2nd Edition
DISC'10 Proceedings of the 24th international conference on Distributed computing
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ICDCN'11 Proceedings of the 12th international conference on Distributed computing and networking
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IEEE Transactions on Parallel and Distributed Systems
DISC'06 Proceedings of the 20th international conference on Distributed Computing
A lazy snapshot algorithm with eager validation
DISC'06 Proceedings of the 20th international conference on Distributed Computing
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Read-write locks are one of the most prevalent lock forms in concurrent applications because they allow read accesses to locked code to proceed in parallel. However, they do not offer any parallelism between reads and writes. This paper introduces pessimistic lock-elision (PLE), a new approach for non-speculatively replacing read-write locks with pessimistic (i.e. non-aborting) software transactional code that allows read-write concurrency even for contended code and even if the code includes system calls. On systems with hardware transactional support, PLE will allow failed transactions, or ones that contain system calls, to preserve read-write concurrency. Our PLE algorithm is based on a novel encounter-order design of a fully pessimistic STM system that in a variety of benchmarks spanning from counters to trees, even when up to 40% of calls are mutating the locked structure, provides up to 5 times the performance of a state-of-the-art read-write lock.