Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Automatic Verification of Parameterized Cache Coherence Protocols
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
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ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Obstruction-Free Synchronization: Double-Ended Queues as an Example
ICDCS '03 Proceedings of the 23rd International Conference on Distributed Computing Systems
Software transactional memory for dynamic-sized data structures
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Shared-memory mutual exclusion: major research trends since 1986
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Transactional Memory Coherence and Consistency
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Unbounded Transactional Memory
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Virtualizing Transactional Memory
Proceedings of the 32nd annual international symposium on Computer Architecture
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Concurrent programming without locks
ACM Transactions on Computer Systems (TOCS)
An effective hybrid transactional memory system with strong isolation guarantees
Proceedings of the 34th annual international symposium on Computer architecture
An integrated hardware-software approach to flexible transactional memory
Proceedings of the 34th annual international symposium on Computer architecture
Model checking transactional memories
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Flexible Decoupled Transactional Memory Support
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Regular model checking without transducers (on efficient verification of parameterized systems)
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Transactional Memory, 2nd Edition
Transactional Memory, 2nd Edition
DISC'06 Proceedings of the 20th international conference on Distributed Computing
Adaptive software transactional memory
DISC'05 Proceedings of the 19th international conference on Distributed Computing
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
VATA: a library for efficient manipulation of non-deterministic tree automata
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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We consider the verification of safety (strict serializability and abort consistency) and liveness (obstruction and livelock freedom) for the hybrid transactional memory framework FlexTM. This framework allows for flexible implementations of transactional memories based on an adaptation of the MESI coherence protocol. FlexTM allows for both eager and lazy conflict resolution strategies. Like in the case of Software Transactional Memories, the verification problem is not trivial as the number of concurrent transactions, their size, and the number of accessed shared variables cannot be a priori bounded. This complexity is exacerbated by aspects that are specific to hardware and hybrid transactional memories. Our work takes into account intricate behaviours such as cache line based conflict detection, false sharing, invisible reads or non-transactional instructions. We carry out the first automatic verification of a hybrid transactional memory and establish, by adopting a small model approach, challenging properties such as strict serializability, abort consistency, and obstruction freedom for both an eager and a lazy conflict resolution strategies. We also detect an example that refutes livelock freedom. To achieve this, our prototype tool makes use of the latest antichain based techniques to handle systems with tens of thousands of states.