Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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Despite the higher scalability and parallelism integration offered by 2D-Network-on-Chip (NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large scale Systems-on-Chip (SoCs). Recently, merging NoC to the third dimension (3D-NoC) has been proposed as a promising solution offering lower power consumption and higher speed. One of the most important design choices for 3D-NoC implementation is the routing algorithm, as it controls the path decision that a flit has tofollow while traveling along the network. This has a direct impact on the overall system performance. In this paper, we present an efficient routing algorithm for 3D-NoC named Look-Ahead-XYZ (LA-XYZ). This algorithm aims to minimize the communication latency and power consumption while enhancing the system throughput. Comparison results with systems adopting two dimensional routing showed that, using JPEG encoder and Matrix applications, LA-XYZ reduces the communication latency with up to 44.9% and enhances the throughput that can reach the 45.3% while observing an average 15.9% reduction in terms of dynamic power.