Adaptive inter-layer message routing in 3D networks-on-chip
Microprocessors & Microsystems
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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In this paper, we propose efficient fault-tolerant routing algorithms for 3D torus with possible large number of faulty nodes. There is no any presumption on the number and the distribution of faulty nodes. The proposed algorithms find a fault-free path between any two nonfaulty nodes with high probability in linear time by using only the local faulty information of the network. The results of our empirical analysis through simulations show that the algorithms can find a fault-free path between any two nonfaulty nodes with a probability higher than 90% in a 3D torus with the number of faulty nodes up to 30%.