A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Clock tree synthesis with pre-bond testability for 3D stacked IC designs
Proceedings of the 47th Design Automation Conference
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Three methods have been proposed to test Through-Silicon-Vias (TSV) electrically prior to 3D integration. These test methods are (1) sense amplification; (2) leakage current monitor; and (3) capacitance bridge methods. These tests are aimed at detecting one or both of two failure types, pin-holes and voids. The test circuits measure capacitance and leakage current of the TSVs, and generate a 1 bit pass/fail signal. The outputs are streamed out through a scan chain. The test time is 10 μs for the leakage test and the sense amplification methods, and is 15 μs for the capacitive bridge method. All these methods can be implemented for test-before-stacking, which will increase assembled yield. Resolution, power and area of these TSV test circuits were compared. The performance of each circuit was studied at PVT corners. The IMEC TSV technology was assumed, and the designs were simulated using the 32 nm predicted device model. Without any failure, the TSV capacitance's mean value is 37 fF, and its leakage resistance is higher than 850 M驴. With respect to 37 fF standard capacitance, resolution for the sense amplification method is 3.3 fF (8.9%); it is 0.16 fF (0.4%) for the capacitance bridge method. Although the capacitance bridge method has relatively better resolution, it takes 4x area and 10x power than the other two, and is also more sensitive to PVT variation. Resolution of the leakage current monitor method is 10 M驴 (1.1%) with respect to its threshold 850 M驴, and use 42.5aJ power in normal case. Sense amplification circuit can be modified to detect equivalent leakage resistance under 2K驴.