Small delay testing for TSVs in 3-D ICs

Authors:
Shi-Yu Huang;Yu-Hsiang Lin;Kun-Han (Hans) Tsai;Wu-Tung Cheng;Stephen Sunter;Yung-Fa Chou;Ding-Ming Kwai
Affiliations:
National Tsing Hua University, Taiwan;National Tsing Hua University, Taiwan;Silicon Test Solutions, Mentor Graphics;Silicon Test Solutions, Mentor Graphics;Silicon Test Solutions, Mentor Graphics;Industrial Technology Research Institute, Taiwan;Industrial Technology Research Institute, Taiwan
Venue:
Proceedings of the 49th Annual Design Automation Conference
Year:
2012

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Abstract

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.