TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Proceedings of the 49th Annual Design Automation Conference
Small delay testing for TSVs in 3-D ICs
Proceedings of the 49th Annual Design Automation Conference
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
Proceedings of the Conference on Design, Automation and Test in Europe
In-situ method for TSV delay testing and characterization using input sensitivity analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation test, in which two TSVs are connected with some peripheral circuit to form an oscillation ring. Upon this foundation, we propose a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in the oscillation ring – a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring’s period. By some following analysis, the propagation delay of each TSV can be revealed. Monte-Carlo analysis of a typical TSV with 30% process variation on transistors shows that the characterization error of this method is only 2.1% with the standard deviation of 8.1%.