Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A rated-clock test method for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Oscillation Ring Delay Test for High Performance Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
All digital built-in delay and crosstalk measurement for on-chip buses
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the measurement of crosstalk in integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
Practical Oscillation-Based Test of Integrated Filters
IEEE Design & Test
Configuration free SoC interconnect BIST methodology
Proceedings of the IEEE International Test Conference 2001
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal
ATS '02 Proceedings of the 11th Asian Test Symposium
Oscillation-test strategy for analog and mixed-signal integrated circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Analyzing Crosstalk in the Presence of Weak Bridge Defects
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Model for Crosstalk Noise Evaluation in Deep Submicron Processes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI
ATS '04 Proceedings of the 13th Asian Test Symposium
Noise-aware buffer planning for interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Small delay testing for TSVs in 3-D ICs
Proceedings of the 49th Annual Design Automation Conference
In-situ method for TSV delay testing and characterization using input sensitivity analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.