A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An empirical study of crosstalk in VDSM technologies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Oscillation ring based interconnect test scheme for SOC
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Crosstalk Induced Fault Analysis and Test in DRAMs
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Single event crosstalk prediction in nanometer technologies
Analog Integrated Circuits and Signal Processing
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Localized delay defects, like resistive shorts, resistiveopens, etc., can be effectively detected by testing the longesttestable path through each wire (or gate) in the circuit. Sucha delay test set is referred to as a longest-path-per-wire testset. ...