Oscillation Ring Delay Test for High Performance Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Proceedings of the IEEE International Test Conference
Analyzing Crosstalk in the Presence of Weak Bridge Defects
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Multilevel full-chip routing with testability and yield enhancement
Proceedings of the 2005 international workshop on System level interconnect prediction
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Small delay testing for TSVs in 3-D ICs
Proceedings of the 49th Annual Design Automation Conference
In-situ method for TSV delay testing and characterization using input sensitivity analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.