Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Analyzing Crosstalk in the Presence of Weak Bridge Defects
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model
Proceedings of the conference on Design, automation and test in Europe
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Single Event crosstalk shielding for CMOS logic
Microelectronics Journal
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Asymptotic waveform evaluation for timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Capacitive coupling noise in high-speed VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling the “Effective capacitance” for the RC interconnect of CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
As CMOS technology continues to scale down, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. On the other hand, coupling effects among interconnects can cause single event transients to contaminate electronically unrelated circuit paths which may increase the SE susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event hardening, modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work, for the first time, proposes an SE crosstalk noise estimation method for use in design automation tools. The proposed method uses an accurate 4-驴 model for interconnect and correctly models the effect of non-switching aggressors as well as aggressor tree branches noting the resistive shielding effect. The SE crosstalk noise expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is about 5.2% while allowing for very fast analysis in comparison to HSPICE.