Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Deterministic tests for detecting single V-coupling faults in RAMs
Journal of Electronic Testing: Theory and Applications
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
A case study of failure analysis and guardband determination for a 64M-bit DRAM
ATS '00 Proceedings of the 9th Asian Test Symposium
Converting March Tests for Bit-Oriented Memories Into Tests for Word-Oriented Memories
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Crosstalk in Deep Submicron DRAMs
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Analyzing Crosstalk in the Presence of Weak Bridge Defects
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Testing Static and Dynamic Faults in Random Access Memories
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This study analyzes the effects of crosstalk-induced faults due to parameter variation during the manufacture of DRAMs. The focus is on read operations, which are sensitive to crosstalk and to neighborhood data patterns. Analytical studies and numerical simulations have been used to investigate a class of crosstalk reading faults (CRF) that read operations are susceptible to. The results reveal that there exist worst case data patterns in each physical RAM block and cell arrangement. The worst case data pattern occurs when neighboring and victim bit-lines switch to opposite values at the same time. If the bit-line arrangement is known, the test for the CRFs is quite trivial. If there is no knowledge of the internal chip structure, a deterministic pattern cannot be assigned and therefore a generic test method is needed. In this paper, a test algorithm is proposed that exhausts every state of any 3 or 5 bit-lines of a RAM block.