Post global routing crosstalk risk estimation and reduction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for river routing with crosstalk constraints
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Full-chip verification of UDSM designs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Predicting coupled noise in RC circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
TAS: an accurate timing analyser for CMOS VLSI
EURO-DAC '91 Proceedings of the conference on European design automation
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults
IEEE Design & Test
Journal of Electronic Testing: Theory and Applications
A multiline model for time-efficient estimation of crosstalk
Analog Integrated Circuits and Signal Processing
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To certify the correctness of a design, in deep submicron technologies, the verification process has to cover some new issues. The noise introduced on signals through the crosstalk coupling is one of these emerging problems. In this paper, we propose a model to evaluate the peak value of the noise injected on a signal during the transition of its neighboring signals. This model has been used in a prototype verification tool and has shown a satisfying accuracy within a reasonable computation delay.