On path selection in combinational logic circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
DESB, a functional abstractor for CMOS VLSI circuits
EURO-DAC '92 Proceedings of the conference on European design automation
Modeling crosstalk noise for deep submicron verification tools
Proceedings of the conference on Design, automation and test in Europe
An Event-Driven Approach to Crosstalk Noise Analysis
ANSS '03 Proceedings of the 36th annual symposium on Simulation
A Model for Crosstalk Noise Evaluation in Deep Submicron Processes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
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A CMOS timing analyser using accurate delay models is presented. Switch-level analytic delays are derived from (I/V) characteristics of short-channel Mosfets. A significant improvement in accuracy is obtained from the analysis of pertinent capacitances, modeling conflicts and slope effects in CMOS gates. The program handles large-scale circuits and gives the worst-case delays between circuit terminals in realistic CPU times. The algorithm of path-analysis is described. It is concluded that the run time is linear with the number of transistors, the accuracy within 5% over a wide range of design types.