On path selection in combinational logic circuits

Authors:
Wing Ning Li;Sudhakar M. Reddy;Sartaj Sahni
Affiliations:
Department of Computer Science, University of Minnesota, Minneapolis, MX;Department of Electrical and Computer Engineering, University, of Iowa, Iowa City, IA;Department of Computer Science, University of Minnesota, Minneapolis, MX
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates signal propagation delays along a set of selected paths are verified to fall within allowed limits by applying appropriate stimuli. Earlier it was suggested that an appropriate set of paths to test would be the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. In this paper, algorithms to select such sets of paths with minimum cardinality are given.