On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Testable path delay fault cover for sequential circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
On path selection in combinational logic circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
On Multiple Path Propagating Tests for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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Existing timing verification tools can provide methodologies for identifying and optimizing critical true paths in an embedded combinational module; however, the problem of justifying these paths to the chip level is a very difficult one. This paper addresses the problem of timing verification at the entire chip level. We use a critical path tool, CRITIC, to obtain critical paths in an embedded combinational module. In order to reduce the complexity of checking whether the module-level critical path is indeed critical at the chip level, we use techniques from formal verification to extract the control behavior of the circuit, and check whether there is any control sequence which will justify the path to the chip level. The results of the experiments on several processor designs show that our approach is very effective in large sequential circuits such as microprocessors, where conventional ATPG techniques require inordinate amounts of CPU time. The experiments also show that the execution time remains reasonable as the circuit size increases, since we deal with a reduced control space rather than the entire state space of the circuit.