Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Test generation for crosstalk-induced faults: framework and computational results
ATS '00 Proceedings of the 9th Asian Test Symposium
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal
ATS '02 Proceedings of the 11th Asian Test Symposium
A fault simulation method for crosstalk faults in synchronous sequential circuits
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Model for Crosstalk Noise Evaluation in Deep Submicron Processes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
International Journal of High Performance Systems Architecture
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This BIST scheme simplifies the detection of crosstalk faults in deep-submicron VLSI circuits in the boundary scan environment. Simulation results show that with just a few random patterns, fault coverage for most large benchmark circuits can exceed 90%.