Generalized de Bruijn digraphs
Networks
Reliable network-on-chip based on generalized de Bruijn graph
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On chip interconnects for multiprocessor turbo decoding architectures
Microprocessors & Microsystems
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In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring, we propose an optimum tile-based implementation for a GBDB-based Network-on-Chip (NoC). Our experimental results show that the latency and energy consumption of generalized de Bruijn graph are much less with compared to Mesh and Torus, the two common NoC architectures in the literature.