VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Turbo Coding
Area-efficient high-speed decoding schemes for turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A parallel pruned bit-reversal interleaver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
An energy-efficient error correction scheme for IEEE 802.15.4 wireless sensor networks
IEEE Transactions on Circuits and Systems II: Express Briefs
Sarnoff'10 Proceedings of the 33rd IEEE conference on Sarnoff
Parallel interleavers through optimized memory address remapping
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On chip interconnects for multiprocessor turbo decoding architectures
Microprocessors & Microsystems
Design and implementation of a linear feedback shift register interleaver for turbo decoding
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.