Parallel interleavers through optimized memory address remapping

Authors:
Jing-Ling Yang
Affiliations:
Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

This work presents mathematical models and collision-free exchange rules for a parallel interleaver, using which it develops an optimized memory address remapping (OPMM) scheme that enables a classic interleaver to be exchanged for a parallel interleaver readily and efficiently. Both analytic and experimental results demonstrate that the rate of annealing achieved using the OPMM approach is much faster than that achieved using the traditional memory address remapping (MM) method.