Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-Decoders
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Computers
A Parallel Decoder Design for Low Latency Turbo Decoding
ICICIC '07 Proceedings of the Second International Conference on Innovative Computing, Informatio and Control
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Sarnoff'10 Proceedings of the 33rd IEEE conference on Sarnoff
Reconfigurable turbo decoder with parallel architecture for 3GPP LTE system
IEEE Transactions on Circuits and Systems II: Express Briefs
Multimode flex-interleaver core for baseband processor platform
Journal of Computer Systems, Networks, and Communications - Special issue on WiMAX, LTE, and WiFi interworking
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Journal of Signal Processing Systems
System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor
International Journal of Embedded and Real-Time Communication Systems
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This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today's consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm2 area in 65 nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.