Error Control Coding, Second Edition
Error Control Coding, Second Edition
A Low Area and Low Power Programmable Baseband Processor Architecture
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
The 802.11n MIMO-OFDM Standard for Wireless LAN and Beyond
Wireless Personal Communications: An International Journal
A Computer Algorithm for Calculating the Product AB Modulo M
IEEE Transactions on Computers
Duo-binary circular turbo decoder based on border metric encoding for WiMAX
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Journal of Signal Processing Systems
IEEE Transactions on Information Theory
A low-cost dual-mode deinterleaver design
IEEE Transactions on Consumer Electronics
A software-defined communications baseband design
IEEE Communications Magazine
Achievable rate of MIMO channels with data-aided channel estimation and perfect interleaving
IEEE Journal on Selected Areas in Communications
A programmable, scalable-throughput interleaver
EURASIP Journal on Wireless Communications and Networking
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This paper presents a flexible interleaver architecture supporting multiple standards like WLAN, WiMAX, HSPA+, 3GPP-LTE, and DVB. Algorithmic level optimizations like 2D transformation and realization of recursive computation are applied, which appear to be the key to reach to an efficient hardware multiplexing among different interleaver implementations. The presented hardware enables the mapping of vital types of interleavers including multiple block interleavers and convolutional interleaver onto a single architecture. By exploiting the hardware reuse methodology the silicon cost is reduced, and it consumes 0.126mm2area in total in 65 nm CMOS process for a fully reconfigurable architecture. It can operate at a frequency of 166 MHz, providing a maximum throughput up to 664 Mbps for a multistream system and 166 Mbps for single stream communication systems, respectively. One of the vital requirements for multimode operation is the fast switching between different standards, which is supported by this hardware with minimal cycle cost overheads. Maximum flexibility and fast switchability among multiple standards during run time makes the proposed architecture a right choice for the radio baseband processing platform.