Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-Decoders
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Multimode flex-interleaver core for baseband processor platform
Journal of Computer Systems, Networks, and Communications - Special issue on WiMAX, LTE, and WiFi interworking
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The interleaver stages of digital communication standards show a surprisingly large variation in throughput, state sizes, and permutation functions. Furthermore, data rates for 4G standards such as LTE-Advanced will exceed typical baseband clock frequencies of handheld devices. Multistream operation for Software Defined Radio and iterative decoding algorithms will call for ever higher interleave data rates. Our interleave machine is built around 8 single-port SRAM banks and can be programmed to generate up to 8 addresses every clock cycle. The scalable architecture combines SIMD and VLIW concepts with an efficient resolution of bank conflicts. A wide range of cellular, connectivity, and broadcast interleavers have been mapped on this machine, with throughputs up to more than 0.5Gsymbol/second. Although it was designed for channel interleaving, the application domain of the interleaver extends also to Turbo interleaving. The presented configuration of the architecture is designed as a part of a programmable outer receiver on a prototype board. It offers (near) universal programmability to enable the implementation of new interleavers. The interleaver measures 2.09mm2 in 65nm CMOS (including memories) and proves functional on silicon.