A parallel pruned bit-reversal interleaver

Authors:
Mohammad M. Mansour
Affiliations:
Electrical and Computer Engineering Department, The American University of Beirut, Beirut, Lebanon and Qualcomm Flarion Technologies, Bridgewater, NJ
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

A parallel algorithm and architecture for pruned bit-reversal interleaving (PBRI) are proposed. For a pruned interleaver of size N with mother interleaver size M = 2n ≥ N, the proposed algorithm interleaves any number x ∈ [0, N-1] in at most n-1 steps, as opposed to x steps using existing PBRI algorithms. A parallel architecture of the proposed algorithm employing simple logic gates and having a short critical path delay is presented. The proposed architecture is valuable in reducing (de-)interleaving latency in emerging wireless standards that employ PBRI channel (de-)interleaving in their PHY layer such as the 3GPP2 Ultra Mobile Broadband standard.