Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Dynamic Access Ordering for Streamed Computations
IEEE Transactions on Computers
Design Issues and Tradeoffs for Write Buffers
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
MisSPECulation: partial and misleading use of SPEC CPU2000 in computer architecture conferences
Proceedings of the 30th annual international symposium on Computer architecture
Efficient use of memory bandwidth to improve network processor throughput
Proceedings of the 30th annual international symposium on Computer architecture
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Modern dram architectures
Adaptive History-Based Memory Schedulers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Memory Controller Optimizations for Web Servers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
A parallel pruned bit-reversal interleaver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access stream increases SDRAM row hit rate, it also increases row conflicts. Mapping of the physical address bits into SDRAM column, row, bank and rank index impacts system performance significantly. A novel address mapping scheme, called bit-reversal, is described and experimentally compared against known methods. The bit-reversal address mapping increases SDRAM row hit rate from 43% to 66% by distributing conflicting memory accesses over independent SDRAM banks. Bit-reversal address mapping reduces the average memory access latency by 26%-29% over other methods, resulting in a 11.7%-13.5% reduction of total execution time. The configuration space of bit-reversal address mapping is explored. Finally, limited studies examining the impact of address mapping techniques in conjunction with SDRAM controller policy and virtual paging illustrate that mapping is better suited to virtual memory free embedded systems than desktop workstations incorporating paging mechanisms.