Parallel lookahead algorithms for pruned interleavers
IEEE Transactions on Communications
A parallel pruned bit-reversal interleaver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 754.84 |
In this paper, we address the issue of pruning (i.e., shortening) a given interleaver in a parallel concatenated convolutional code (PCCC). The principle goal of pruning is that of construction of variable-length and hence delay interleavers with application to PCCC, using the same structure (possibly in hardware) of the interleaver and deinterleaver units. As a side benefit, it is sometimes possible to reduce the interleaver length and hence delay for nearly the same and sometimes even better asymptotic performance. In particular, we present a systematic technique for interleaver pruning and demonstrate the average optimality of the strategy. Sample simulation results are presented confirming the average optimality of the proposed scheme.