In-place memory management of algebraic algorithms on application specific ICs
Journal of VLSI Signal Processing Systems - Special issue: algorithms and parallel VSLI architecture
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
IPPS '99/SPDP '99 Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing
Fast Computational Algorithms for Bit Reversal
IEEE Transactions on Computers
Parallel lookahead algorithms for pruned interleavers
IEEE Transactions on Communications
A parallel pruned bit-reversal interleaver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified fast recursive algorithm for data shuffling in variousorders
IEEE Transactions on Signal Processing
Fast bit-reversal algorithms based on index representations in GF(2b)
IEEE Transactions on Signal Processing
A better FFT bit-reversal algorithm without tables
IEEE Transactions on Signal Processing
Bit reversal in FFT from matrix viewpoint
IEEE Transactions on Signal Processing
A new efficient computational algorithm for bit reversal mapping
IEEE Transactions on Signal Processing
Efficient Bit and Digital Reversal Algorithm Using Vector Calculation
IEEE Transactions on Signal Processing
New FFT bit-reversal algorithm
IEEE Transactions on Signal Processing
Design of fast-prunable S-random interleavers
IEEE Transactions on Wireless Communications
Realization of optimum interleavers
IEEE Transactions on Information Theory
Interleavers for turbo codes using permutation polynomials over integer rings
IEEE Transactions on Information Theory
Multicarrier modulation for data transmission: an idea whose time has come
IEEE Communications Magazine
An efficient parallel-processing method for transposing large matrices in place
IEEE Transactions on Image Processing
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In this paper, pruned bit-reversal permutations employed in variable-length interleavers and their associated fast pruning algorithms and architectures are considered. Pruning permutations is mathematically formulated as a counting problem in a set of k integers and any subset of $\alpha $ consecutive integers under some permutation, where integers from this subset that map into indices less than some $\beta are to be counted. A solution to this problem using sums involving integer floors and related functions is proposed. It is shown that these sums can be evaluated recursively using integer operations. Specifically, a mathematical treatment for bit-reversal permutations (BRPs) and their permutation statistics are presented. These permutations have been mainly addressed using numerical techniques in the literature to speed up in-place computations of fast Fourier and related transforms. Closed-form expressions for BRP statistics including inversions, serial correlations, and a new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers, are derived. Using the inliers statistic, a recursive algorithm that computes the minimum number of inliers in a pruned BR interleaver (PBRI) in logarithmic time complexity is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers are also presented. Moreover, efficient hardware architectures for the proposed algorithms employing simple logic gates are presented. Simulation results of interleavers employed in modern communication standards demonstrate 3 to 4 orders of magnitude improvement in interleaving time compared to existing approaches.