Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback
IEEE Transactions on Computers
Hierarchical Checking of Multiprocessors Using Watchdog Processors
EDCC-1 Proceedings of the First European Dependable Computing Conference on Dependable Computing
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
A tool for automatic generation of self-checking data paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Soft-Error Detection Using Control Flow Assertions
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Proceedings of the 12th ACM conference on Computer and communications security
Probabilistic arithmetic and energy efficient embedded signal processing
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
Watchdog Processors and Structural Integrity Checking
IEEE Transactions on Computers
A case study in reliability-aware design: a resilient LDPC code decoder
Proceedings of the conference on Design, automation and test in Europe
Concepts for Autonomous Control Flow Checking for Embedded CPUs
ATC '08 Proceedings of the 5th international conference on Autonomic and Trusted Computing
Hardware-assisted run-time monitoring for secure program execution on embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs
International Journal of Autonomous and Adaptive Communications Systems
RAS strategy for IBM S/390 G5 and G6
IBM Journal of Research and Development
From parallelism levels to a multi-ASIP architecture for turbo decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and architectures for dependable embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A case study on error resilient architectures for wireless communication
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
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Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only profitable if the costs in terms of area, energy and delay for reliability keep within limits. Therefore, the traditional worst case design methodology will become infeasible. Future architectures have to be error resilient, i.e., the hardware architecture has to tolerate autonomously transient errors. In this paper, we present an FPGA based rapid prototyping system for multi-processor systems-on-chip composed of autonomous hardware units for error-resilient processing and interconnect. This platform allows the fast architectural exploration of various error protection techniques under different failure rates on the microarchitectural level while keeping track of the system behavior. We demonstrate its applicability on a concrete wireless communication system.