Checkpoint repair for out-of-order execution machines
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
Reliability Issues in Computing System Design
ACM Computing Surveys (CSUR)
Automated micro-roll-back self-recovery synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Compiler-Based Multiple Instruction Retry
IEEE Transactions on Computers
Rapid prototyping of fault-tolerant VLSI systems
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Self recovering controller and datapath codesign
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures
IEEE Transactions on Parallel and Distributed Systems
Operating system level support for coherence in distributed systems
EW 5 Proceedings of the 5th workshop on ACM SIGOPS European workshop: Models and paradigms for distributed systems structuring
Computer-Aided Design of Fault-Tolerant VLSI Systems
IEEE Design & Test
Transient Fault Tolerance in Digital Systems
IEEE Micro
Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer
IEEE Transactions on Computers
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
The Performance of Cache-Based Error Recovery in Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A Fault Tolerant Approach to Microprocessor Design
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
High-Level Synthesis of Recoverable Microarchitectures
EDTC '96 Proceedings of the 1996 European conference on Design and Test
14.1 Fast Self-Recovering Controllers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
An Efficient On-line-Test and Back-up Scheme for Embedded Processors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An error recoverable structure based on complementary logic and alternating-retry
Journal of Computer Science and Technology
Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices
IEEE Transactions on Computers
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Improving chip multiprocessor reliability through code replication
Computers and Electrical Engineering
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast online error detection and correction with thread signature calculae
Microprocessors & Microsystems
| Hi-index | 14.99 |
A technique called micro rollback, which allows most of the performance penalty for concurrent error detection to be eliminated, is presented. Detection is performed in parallel with the transmission of information between modules, thus removing the delay for detection from the critical path. Erroneous information may thus reach its destination module several clock cycles before an error indication. Operations performed on this erroneous information are undone using a hardware mechanism for fast rollback of a few cycles. The implementation of a VLSI processor capable of micro rollback is discussed, as well as several critical issues related to its use in a complete system.