Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
A measurement-based model for workload dependence of CPU errors
IEEE Transactions on Computers - The MIT Press scientific computation series
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
Advanced compiler optimizations for supercomputers
Communications of the ACM - Special issue on parallelism
A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback
IEEE Transactions on Computers
Selected papers of the second workshop on Languages and compilers for parallel computing
Design of the IBM Enterprise System/9000 high-end processor
IBM Journal of Research and Development
Fault-tolerance design of the IBM Enterprise System/9000 Type 9021 processors
IBM Journal of Research and Development
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Compiler-Based Multiple Instruction Retry
IEEE Transactions on Computers
Incremental compiler transformations for multiple instruction retry
Software—Practice & Experience
Simulation/evaluation environment for a VLIW processor architecture
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
MPS: Miss-Path Scheduling for Multiple-Issue Processors
IEEE Transactions on Computers
Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer
IEEE Transactions on Computers
Generalized Multiway Branch Unit for VLIW Microprocessors
IEEE Transactions on Parallel and Distributed Systems
A Development Environment for Horizontal Microcode
IEEE Transactions on Software Engineering
G4: A Fault-Tolerant CMOS Mainframe
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
An Eight Issue Tree-VLIW Processor for Dynamic Binary Translation
ICCD '98 Proceedings of the International Conference on Computer Design
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
An error recoverable structure based on complementary logic and alternating-retry
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
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Very Long Instruction Word (VLIW) architectures can enhance performance by exploiting fine-grained instruction level parallelism. In this paper, we describe a compiler assisted multiple instruction word retry scheme for VLIW architectures. A read buffer is used to resolve the more frequent on-path hazards, while the compiler resolves the remaining branch hazards. Performance evaluation is described for 11 benchmark programs based on the IBM VLIW research compiler, Chameleon. Experimental results indicate that, for a VLIW machine with P functional units to rollback N instruction words, a read buffer of 2NP entries with the compiler assist can be an effective approach in producing low overhead runtime performance and small code growth, for P = 4, 8, 12, and 16 and N \leq 3.