Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
Adding error-correcting circuitry to ASIC memory
IEEE Spectrum
Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures
IEEE Transactions on Parallel and Distributed Systems
Soft Errors in Advanced Computer Systems
IEEE Design & Test
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
Error-correcting codes for semiconductor memory applications: a state-of-the-art review
IBM Journal of Research and Development
Improving cache lifetime reliability at ultra-low voltages
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low-Power, Resilient Interconnection with Orthogonal Latin Squares
IEEE Design & Test
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
Towards a tool for implementing delay-free ECC in embedded memories
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
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Drastic device shrinking, power supply reduction, increasing complexity and increasing operating speeds affect adversely the reliability of nowadays Integrate Circuits (ICs). In many modern designs, embedded memories occupy the largest part of the die and comprise the large majority of transistors. Furthermore, memories are designed as tight as allowed by the process, and are therefore more prone to failures than other circuits. Error correcting codes (ECCs) are an efficient mean for protecting memories against failures. A major drawback of ECCs is the speed penalty induced by the encoding and decoding circuits. In this paper, we present an architecture enabling implementing ECCs without speed penalty. Furthermore, as the manual implementation of this solution is impractical for complex System-on-Chips (SoCs), we propose an algorithm and a set of generic rules allowing automatic insertion of the delay-free ECCs in any complex architecture at Register Transfer Level (RTL). With respect to a naive insertion in the design of the new architecture, the algorithm enable up to 20 % hardware reduction. The Finite State Machines (FSM) that controls the new ECC architecture is also generated automatically. Experimental evaluations show that the hardware overhead of the speed penalty free ECCs protected memory compared to a standard implementation of ECC protected memory is about 2.5 % with an additional power consumption of 6 %.