Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback
IEEE Transactions on Computers
IMPACT: an architectural framework for multiple-instruction-issue processors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Compiler-assisted multiple instruction rollback recovery using a read buffer
Compiler-assisted multiple instruction rollback recovery using a read buffer
Compiler-Based Multiple Instruction Retry
IEEE Transactions on Computers
Application of Compiler-Assisted Rollback Recovery to Speculative Execution Repair
Revised Papers from a Workshop on Hardware and Software Architectures for Fault Tolerance
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Graph Theory With Applications
Graph Theory With Applications
Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures
IEEE Transactions on Parallel and Distributed Systems
An error recoverable structure based on complementary logic and alternating-retry
Journal of Computer Science and Technology
Hi-index | 14.98 |
Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compiler-based MIR designs have also been developed which remove rollback data hazards directly with data-flow transformations. This paper describes compiler-assisted techniques to achieve multiple instruction rollback recovery. We observe that some data hazards resulting from instruction rollback can be resolved efficiently by providing an operand read buffer while others are resolved more efficiently with compiler transformations. The compiler-assisted scheme presented consists of hardware that is less complex than shadow files, history files, history buffers, or delayed write buffers, while experimental evaluation indicates performance improvement over compiler-based schemes.